1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a fine-structured connection layer.
2. Description of the Related Art
Recently, a semiconductor devices have been fine-structured. For example, a 0.5 .mu.m rule is adopted in a 16 Mbit dynamic random access memory (DRAM), and a 0.3 to 0.35 .mu.m rule will be adopted in a 64 Mbit DRAM. As semiconductor devices have become more fine-structured, metal connections, and openings such as contact holes and through holes have also become more fine-structured.
Although an aluminium metal connection layer has a high conductivity, the aluminium connection layer has a small life-time due to the stress migration caused by the fine-structure thereof. To avoid this, a stacked configuration metal layer has been suggested. For example, a double configuration metal layer is formed by a lower metal layer made of high melting temperature metal such as titanium tungsten and an upper metal layer made of high conductivity metal such as aluminium. Also, a triple configuration metal layer is formed by a lower metal layer made of high melting temperature metal such as titanium tungsten, a middle metal layer made of high conductivity metal such as aluminium, and an upper metal layer made of high melting temperature metal such as titanium tungsten. Further, in order to improve a step coverage characteristic for openings such as contact holes or through holes, a tungsten layer deposited by a chemical vapor deposition (CVD) process is inserted between the lower metal layer and the upper metal layer in the double configuration and between the lower metal layer and the middle metal layer in the triple configmation.
In a prior art method for manufacturing a stacked connection layer, a photoresist layer is coated on a stacked metal layer formed by at least a lower metal layer and an upper metal layer, and the photoresist layer is patterned by a photolithography process. Then, the upper metal layer is etched with a mask of the patterned photoresist layer, and after that, the lower metal layer is etched with a mask of the same pattern photoresist layer and the upper metal layer, which will be later explained in more detail.
In the above-mentioned prior art manufacturing method, since the patterned photoresist layer is exposed to etching gas at least twice, it is impossible to obtain an accurate selection ratio (etching ratio) of the final stacked connection layer to the insulating layer, as will be explained later. As a result, the size of the stacked connection layer is reduced as compared with that of the original patterned photoresist layer. Particularly, the width of the stacked connection layer is reduced so as to reduce the conductivity thereof, thus inviting stress migration.
Also, if an opening such as a contact hole or a through hole is provided and is connected to the lower metal layer, the patterned photoresist layer at a final etching process may be deviated from the location of the opening, as the etching process progresses. As a result, if a part of the lower metal layer filled in the opening may be etched, and also, at worst, if an impurity region formed within a semiconductor substrate at the opening may be etched, a defective connection such as a disconnection or low conductivity at a contact portion, an increase of junction leakage in the impurity region, a reduction of duration of a junction portion, and the like may occur.
Further, since the patterned photoresist layer is exposed to etching gas for a long time, the contact characteristic of the photoresist layer to the stacked connection layer is deteriorated, thus deteriorating the etching operation.